Memory system with multiple open rows per bank

A method of controlling a memory component, comprising:

• receiving information, from a memory component, associating row addresses of a DRAM device to respective indicators that are to be set to a first value in response to commands to the memory component to open rows, the respective indicators associated with a respective plurality of row address segments, the row address segments corresponding to respective row address ranges;
• and,
• setting a plurality of the respective indicators to the first value, the plurality of the respective indicators are set to the first value in response to at least the memory controller processing a command to the memory component to open a first row in the respective row address range associated with at least one of the respective indicators, the first value being associated with the respective associated row address segments being unavailable for opening a second row in the associated respective row address range.

A memory controller, comprising:

• control circuitry to set to a first value, respective indicators in an address table that associates respective indicators with a respective plurality of row address segments, the row address segments corresponding to respective row address ranges, the first value to be associated with the respective row address segment being unavailable for opening a row in the associated respective row address range, where a plurality of the respective indicators are set to the first value in response to at least the memory controller processing a command to a memory component to open a row in the respective row address range associated with at least one of the respective indicators;
• and,
• configuration reading circuitry to receive configuration information, from the memory component, that associates row addresses to respective indicators that are to be set to the first value in response to the command to the memory component to open a row.