Efficient ferroelectric random-access memory wordline driver, decoder, and related circuits

A wordline driver, comprising:

• an input node connected to an output of a wordline decoder and configured to receive an input signal from the wordline decoder;
• a first complementary pair of transistors connected to the input node and configured to provide an inverse of the input signal to an internal node of the wordline driver in a first power domain;
• and
• a second complementary pair of transistors in a second power domain and configured to receive the inverse of the input signal and to output a re-inverted version of the input signal to a wordline,
• wherein the second complementary pair is configured to provide the re-inverted version of the input signal at a boosted voltage.

A circuit, comprising:

• a wordline decoder connected to an input voltage source and having an output configured to provide a selection signal;
• an input node connected to an output of the wordline decoder;
• a first transistor having a first node connected to the input node and a second node connected to the input voltage source;
• a second transistor having a first node connected to the input node, a second node connected to a third node of the first transistor at an internal node, and a third node connected to ground;
• a third transistor having a first node connected to the internal node, a second node connected to a boosted voltage source, and a third node connected to a wordline;
• a fourth transistor having a first node connected to the internal node, a second node connected to the wordline, and a third node connected to ground;
• a fifth transistor having a first node connected to the wordline, a second node connected to the boosted voltage source, and a third node connected to the internal node;
• and
• a sixth transistor connected at a first node to the first transistor and the second transistor and at a second node to the internal node.