Integrated circuit with thicker metal lines on lower metallization layer

An integrated circuit (IC) structure, comprising:

• a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
• a first metallization layer above the first, second, third and fourth transistors, the first metallization layer comprising a plurality of first metal lines extending laterally along a first direction and arranged at a first line-to-line spacing, wherein the plurality of first metal lines each have a first length measured along the first direction, and one or more of the plurality of first metal lines are part of a first net electrically connecting the first transistor and the second transistor;
• and
• a second metallization layer over the first metallization layer, the second metallization layer comprising a plurality of second metal lines extending laterally along a second direction perpendicular to the first direction and arranged at a second line-to-line spacing, wherein the plurality of second metal lines each have a second length measured along the second direction, the first line-to-line spacing is greater than the second line-to-line spacing, one or more of the plurality of second metal lines are part of a second net connecting the third transistor and the fourth transistor, and a total length of the second lengths of the plurality of second metal lines in the second net is less than a total length of the first lengths of the plurality of first metal lines in the first net.

An integrated circuit (IC) structure, comprising:

• a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
• a first metallization layer above the first, second, third and fourth transistors, the first metallization layer having a plurality of first metal lines extending laterally along a first direction and having a first line height measured vertically in a second direction perpendicular to the first direction, wherein the plurality of first metal lines each have a first length measured along the first direction, and one or more of the plurality of first metal lines are part of a first net electrically connecting the first transistor and the second transistor;
• and
• a second metallization layer over and next to the first metallization layer, the second metallization layer having a plurality of second metal lines extending laterally along a third direction perpendicular to the first and second directions, the plurality of second metal lines having a second line height measured vertically in the second direction, wherein the plurality of second metal lines each have a second length measured along the third direction, the second line height of the plurality of second metal lines is less than the first line height of the plurality of first metal lines, one or more of the plurality of second metal lines are part of a second net electrically connecting the third transistor and the fourth transistor, and a total length of the second length of the plurality of second metal lines in the second net is less than a total length of the first length of the plurality of first metal lines in the first net.