Dual mode interconnect

A method, comprising:

• configuring a first slave port and a first master port in a streaming interconnect in a circuit switching mode, each of the first slave port and the first master port being connected to another respective component exterior to the streaming interconnect, wherein, when configured in the circuit switching mode, first streaming data routed through the first slave port and the first master port is deterministic;
• configuring a second slave port and a second master port in the streaming interconnect in a packet switching mode, each of the second slave port and the second master port being connected to another respective component exterior to the streaming interconnect, wherein, when configured in the packet switching mode, second streaming data routed through the second slave port and the second master port is non-deterministic;
• and
• transmitting data between a first data processing engine in an array of data processing engines in a SoC and a second data processing engine in the array of data processing engines using the streaming interconnect;
• wherein the first master port and the first slave port cannot be shared by multiple logical streams;
• and
• wherein the second master port and the second slave port are capable of being shared by multiple logical streams.

An integrated circuit comprising:

• a plurality of data processing engines (DPEs), each DPE of the plurality of DPEs comprising:
• a streaming interconnect comprising ports, respective ones of the ports being connected to a port of another streaming interconnect of another DPE of the plurality of DPEs, each port of the ports being programmable based on data written to a configuration register to be coupled to one or more ports of the ports to communicate streaming data selectively in a circuit switching mode and a packet switching mode,
• wherein, when programmed to be in the circuit switching mode, streaming data communicated through and between respective ports of the ports in the streaming interconnect is deterministic,
• wherein, when programmed to be in the packet switching mode, streaming data communicated through and between respective ports of the ports in the streaming interconnect is non-deterministic, and
• wherein for each streaming interconnect of the streaming interconnects, each port of the ports of the respective streaming interconnect:
• when programmed to be in the circuit switching mode, cannot be shared by multiple logical streams;
• and
• when programmed to be in the packet switching mode, is capable of being shared by multiple logical streams.