Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller

An apparatus comprising:

• a high-speed fabric controller comprising a data tiering aggregator;
• a memory controller connected between a high-speed memory and a processor, the memory controller configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory;
• a high-speed data connection between the memory controller and the high-speed fabric controller;
• a data connection between a first tier of persistent data storage and the high-speed fabric controller;
• and
• a data connection between each of one or more additional tiers of persistent data storage and the high-speed fabric controller;
• a data connection between the processor and the high-speed fabric controller,
• wherein the data tiering aggregator is configured to control data tiering between the high-speed memory, the first tier of persistent data storage and the one or more additional tiers of persistent data storage, and
• wherein the high-speed fabric controller is configured to control data transfers between the first tier of persistent data storage and the high-speed memory independent of the processor without the data passing through the processor.

A system comprising:

• a processor;
• a high-speed memory connected to the processor over a memory bus;
• a high-speed fabric controller;
• a memory controller connected between the high-speed memory and the processor, the memory controller configured to control processor access to the high-speed memory over the memory bus;
• a data connection between the processor and the high-speed fabric controller;
• a high-speed data connection between the memory controller and the high-speed fabric controller;
• and
• a data connection between each of one or more tiers of persistent data storage and the high-speed fabric controller,
• wherein the high-speed data connection between the memory controller and the high-speed fabric controller is separate from the connection between the processor and the high-speed fabric controller, and
• wherein the high-speed fabric controller is configured to control data transfers between the one or more tiers of persistent data storage and the high-speed memory independent of the processor.