Realm identifier comparison for translation cache lookup

An apparatus comprising:

• a translation cache comprising a plurality of entries, each entry to specify address translation data for a corresponding memory region, a translation context identifier identifying a translation context associated with the address translation data, and a realm identifier identifying one of a plurality of realms, each realm corresponding to at least a portion of at least one software process executed by processing circuitry;
• and
• control circuitry to trigger a lookup of the translation cache in response to a memory access to a target memory region issued from a current translation context and a current realm;
• wherein when the lookup misses in the translation cache, the control circuitry is configured to prevent allocation of address translation data to the translation cache in response to the memory access when the current realm is excluded from accessing the target memory region by an owner realm specified from among the plurality of realms for the target memory region;
• and
• in the lookup, the control circuitry is configured to determine whether said memory access matches a given entry of the translation cache in dependence on a first comparison between the translation context identifier specified by the given entry and a translation context identifier of said current translation context and a second comparison between the realm identifier specified by the given entry and a realm identifier of said current realm.

A non-transitory storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment comprising:

• a translation cache comprising a plurality of entries, each entry to specify address translation data for a corresponding memory region, a translation context identifier identifying a translation context associated with the address translation data, and a realm identifier identifying one of a plurality of realms, each realm corresponding to at least a portion of at least one software process in the instruction execution environment;
• and
• control program logic to trigger a lookup of the translation cache in response to a memory access to a target memory region issued from a current translation context and a current realm in the instruction execution environment;
• wherein when the lookup misses in the translation cache, the control program logic is configured to prevent allocation of address translation data to the translation cache in response to the memory access when the current realm is excluded from accessing the target memory region by an owner realm specified from among the plurality of realms for the target memory region;
• and
• in the lookup, the control program logic is configured to determine whether said memory access matches a given entry of the translation cache in dependence on a first comparison between the translation context identifier specified by the given entry and a translation context identifier of said current translation context and a second comparison between the realm identifier specified by the given entry and a realm identifier of said current realm.