Shared buffered memory routing

An apparatus comprising:

• a first device comprising at least a portion of an interconnect fabric, a first shared memory controller to control access to first shared memory, and a first plurality of processor nodes, wherein the first device further comprises an interface to receive a data request from a second device over a data link, the interface comprises physical layer circuitry to implement a physical layer for the data link according to a physical layer protocol, and the interface further comprises first link layer circuitry to implement a first link layer protocol and second link layer circuitry to implement a different second link layer protocol,
• wherein the data link comprises a plurality of lanes, the data link supports multiplexing of data of the different first and second link layer protocols over the same physical layer of the data link, the first shared memory is not directly connected to the processor nodes, and the second device comprises a second shared memory controller to couple and control access to second shared memory, and a second plurality of processor nodes,
• wherein the data request comprises link layer data, the data request is addressed to be routed to the first memory controller through the interconnect fabric from the second device, and the first memory controller is to handle the data request, wherein the data request comprises a node identifier to identify a particular processor node of the second plurality of processor nodes as a source of the data request, and the data request further comprises an address to identify a portion of the first shared memory associated with the data request.