Processing system, related integrated circuit and method
AssigneeStmicroelectronics Application GmbH
InventorRoberto Colombo
Life of this patent
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Abstract
A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
Claims20
A processing system, comprising:
- a plurality of circuits configured to produce a plurality of error signals, each of the plurality of circuits being configured to generate a respective error signal of the plurality of error signals;
- a first error pad;
- a second error pad;
- and
- a fault collection circuit configured to receive, at an input of the fault collection circuit, the plurality of error signals and configured to generate a combined error signal for the first error pad and a combined error signal for the second error pad, wherein the fault collection circuit comprises:
- a first combinational logic circuit configured to generate the combined error signal for the first error pad and the combined error signal for the second error pad, the combined error signal for the first error pad comprising a first selection of error signals and the combined error signal for the second error pad comprising a second selection of error signals, the first selection of error signals and the second selection of error signals being selected as a function of a first set of configuring bits.
An integrated circuit, comprising:
- a processing system, comprising:
- a plurality of circuits configured to produce a plurality of error signals, each of the plurality of circuits being configured to generate a respective error signal of the plurality of error signals;
- a first error pad;
- a second error pad;
- and
- a fault collection circuit configured to receive, at an input of the fault collection circuit, the plurality of error signals and configured to generate a combined error signal for the first error pad and a combined error signal for the second error pad, wherein the fault collection circuit comprises:
- a first combinational logic circuit configured to generate the combined error signal for the first error pad and the combined error signal for the second error pad, the combined error signal for the first error pad comprising a first selection of error signals and the combined error signal for the second error pad comprising a second selection of error signals, the first selection of error signals and the second selection of error signals being selected as a function of a first set of configuring bits.
A method of operating a processing system, the method comprising:
- providing a first set of configuring bits to the processing system;
- generating, via a plurality of circuits of the processing system, at least one error signal;
- receiving, at an input of a fault collection circuit of the processing system, the at least one error signal;
- and
- generating, via the fault collection circuit, a respective combined error signal for a first error pad of the processing system by selectively routing the at least one error signal to the first error pad as a function of a first set of configuring bits;
- and
- generating, via the fault collection circuit, a combined error signal for a second error pad of the processing system by selectively routing the at least one error signal to the second error pad as a function of the first set of configuring bits.
Dependencies are inferred from the claim text.