Real time block failure analysis for a memory sub-system
AssigneeMicron Technology, Inc.
InventorsFrancis Chew, Gerald L. Cadloni, Bruce A. Liikanen
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsFrancis Chew, Gerald L. Cadloni, Bruce A. Liikanen
Estimating the term…
Several embodiments of memory devices and systems for real time block failure analysis are disclosed herein. In one embodiment, a system includes a memory array including a plurality of memory cells and a processing device coupled to the memory array. The processing device is configured to sense, in response to detection of an error associated with a subset of a plurality of memory cells of the memory device, a state associated with each memory cell of the subset of the plurality of memory cells. The processing device is further configured to store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset.
A system comprising:
A method for storing state information of a memory region of a system, the method comprising:
A non-transitory computer readable medium having instructions stored thereon that, upon execution by a computing device, cause the computing device to perform operations, wherein the instructions comprise:
Dependencies are inferred from the claim text.