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US 11,113,073 B2Granted
Dual mode hardware reset
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
Estimating the term…
Abstract
Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.
Claims22
A host system comprising:
- a host device comprising a host processor;
- a storage system comprising at least one non-volatile memory device, control circuitry coupled to the non-volatile memory device, and a storage register to store at least one control bit;
- and
- a communication interface between the host device and the storage system;
- and
- a reset interface between the host device and the storage system,
- wherein the host device is configured to control a power mode of the storage system, the power mode comprising an operational mode and a low power mode in which the communication interface is disabled,
- wherein, in the low power mode, the control circuitry is configured to provide one of a first reset or a second reset to transition to the storage system from the low power mode to the operational power mode in response to a reset signal from the host device on the reset interface and a value of the at least one control bit,
- wherein, in the operational power mode, the host processor is configured to control the value of the at least one control bit, and
- wherein, in the low power mode, the control circuitry is configured to control the value of the at least one control bit.
7 more elements
A system comprising:
- a storage system comprising a group of non-volatile memory cells, control circuitry coupled to the group of non-volatile memory cells, and at least one control bit,
- wherein, in an operational power mode of the storage system, the control circuitry is configured to communicate with a host device through a bidirectional communication interface,
- wherein, in a low power mode of the storage system, the control circuitry is configured to provide one of a first reset or a second reset to transition to the storage system from the low power mode to the operational power mode in response to a hardware reset signal and a value of the at least one control bit,
- wherein the value of the at least one control bit is controlled by the host device in the operational power mode of the storage system and by the storage system in the low power mode of the storage system.
1 more element
A method implemented by control circuitry of a storage system, the method comprising:
- receiving, in a low power mode of the storage system, a hardware reset signal from a host device;
- and
- providing one of a first reset or a second reset to transition to the storage system from the low power mode to an operational power mode in response to the received hardware reset signal and a value of at least one control bit on the storage system,
- wherein the value of the at least one control bit is controlled by the host device in the operational power mode and the storage system in the low power mode.
1 more element
A non-transitory machine-readable medium, storing instructions, which when executed by a storage system, cause the storage system to perform operations comprising:
- receiving, in a low power mode of the storage system, a hardware reset signal from a host device;
- and
- providing one of a first reset or a second reset to transition to the storage system from the low power mode to an operational power mode in response to the received hardware reset signal and a value of at least one control bit on the storage system,
- wherein the value of the at least one control bit is controlled by the host device in the operational power mode and the storage system in the low power mode.
1 more element
Dependencies are inferred from the claim text.