Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)

A method for performing flush recovery using parallel walks of sliced reorder buffers (SROBs), the method comprising:

• detecting, by a register mapping circuit of a processor device, an uncommitted instruction within an execution pipeline of the processor device, the uncommitted instruction comprising a write instruction to a destination logical register number (LRN) among a plurality of LRNs, wherein the register mapping circuit comprises a reorder buffer (ROB);
• allocating, to the uncommitted instruction, an SROB slice entry among a plurality of SROB slice entries of an SROB slice corresponding to the destination LRN among a plurality of SROB slices of an SROB of the processor device, wherein each SROB slice of the plurality of SROB slices is configured to track only uncommitted instructions that write to a respective LRN among the plurality of LRNs;
• receiving an indication of a pipeline flush from a target instruction within the execution pipeline;
• and
• responsive to receiving the indication of the pipeline flush, restoring a plurality of rename map table (RMT) entries of an RMT to a corresponding plurality of prior mapping states, based on sequential accesses, performed in parallel, of the plurality of SROB slices corresponding to LRNs of the plurality of RMT entries.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device, cause the processor device to:

• detect an uncommitted instruction within an execution pipeline of the processor device, the uncommitted instruction comprising a write instruction to a destination logical register number (LRN) among a plurality of LRNs, wherein the processor device comprises a reorder buffer (ROB);
• allocate, to the uncommitted instruction, a sliced reorder buffer (SROB) slice entry among a plurality of SROB slice entries of an SROB slice corresponding to the destination LRN among a plurality of SROB slices of an SROB of the processor device, wherein each SROB slice of the plurality of SROB slices is configured to track only uncommitted instructions that write to a respective LRN among the plurality of LRNs;
• receive an indication of a pipeline flush from a target instruction within the execution pipeline;
• and
• responsive to receiving the indication of the pipeline flush, restore a plurality of rename map table (RMT) entries of an RMT to a corresponding plurality of prior mapping states, based on sequential accesses, performed in parallel, of the plurality of SROB slices corresponding to LRNs of the plurality of RMT entries.