Automated concurrency and repetition with minimal syntax

A computer-program product tangibly embodied in a non-transitory machine-readable storage medium, the computer-program product including instructions operable to cause a first processor core to perform operations comprising:

• receiving a request to execute executable instructions of application code that comprises an instruction block and a trigger instruction, wherein:
• the instruction block comprises executable instructions operable to cause a second processor core to perform operations comprising:
• reading a single row of data values from a first data structure;
• and
• outputting at least one data value generated by a performance of a function using the single row as an input;
• the first data structure is divided into multiple portions that each comprise multiple rows;
• and
• the trigger instruction serves to provide an indication that:
• multiple instances of the instruction block that correspond to the multiple portions of the first data structure are to be executed concurrently;
• and
• each instance of the instruction block is to be executed repetitively until all rows of the corresponding portion of the first data structure are used as input to the function, wherein the repetitive execution of each instance commences independently of the other instances and completes independently of the other instances;
• and
• in response to the request, and in response to identification of the instruction block and the trigger instruction as present within the application code, performing operations comprising:
• generating multiple instances of a support block corresponding to the multiple instances of the instruction block, wherein each instance of the support block comprises executable instructions operable to cause the second processor core to execute a corresponding instance of the instruction block repetitively until all rows of the corresponding portion of the first data structure are used as input to the function;
• assigning each instance of the instruction block and corresponding support block to be executed by a processor core of a set of processor cores, wherein the set of processor cores comprises the second processor core;
• and
• providing each instance of the instruction block with access to the corresponding portion of the first data structure.

A computer-implemented method comprising:

• receiving, by a first processor core, a request to execute executable instructions of application code that comprises an instruction block and a trigger instruction, wherein:
• the instruction block comprises executable instructions operable to cause a second processor core to perform operations comprising:
• reading a single row of data values from a first data structure;
• and
• outputting at least one data value generated by a performance of a function using the single row as an input;
• the first data structure is divided into multiple portions that each comprise multiple rows;
• and
• the trigger instruction serves to provide an indication that:
• multiple instances of the instruction block that correspond to the multiple portions of the first data structure are to be executed concurrently;
• and
• each instance of the instruction block is to be executed repetitively until all rows of the corresponding portion of the first data structure are used as input to the function, wherein the repetitive execution of each instance commences independently of the other instances and completes independently of the other instances;
• and
• in response to the request, and in response to identification of the instruction block and the trigger instruction as present within the application code, performing operations comprising:
• generating, by the first processor core, multiple instances of a support block corresponding to the multiple instances of the instruction block, wherein each instance of the support block comprises executable instructions operable to cause the second processor core to execute a corresponding instance of the instruction block repetitively until all rows of the corresponding portion of the first data structure are used as input to the function;
• assigning, by the first processor core, each instance of the instruction block and corresponding support block to be executed by a processor core of a set of processor cores, wherein the set of processor cores comprises the second processor core;
• and
• providing, by the first processor core, each instance of the instruction block with access to the corresponding portion of the first data structure.