Store instruction to store instruction dependency

A system for creating a store instruction dependency in a processor pipeline, the system comprising:

• a processor communicatively coupled to a memory, the processor configured to:
• detect a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction;
• compare the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
• write a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
• analyze, prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction;
• and
• delay the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction,
• wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises:
• translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction,
• translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and
• comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction.

A computer program product for creating a store instruction dependency in a processor pipeline, the computer product comprising a computer readable storage medium having program instructions embodied therewith, the instructions executable by a processor to cause the processor to:

• detect a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction;
• compare the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
• write a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction;
• analyze, prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction;
• and
• delay the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction,
• wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises:
• translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction,
• translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and
• comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction.