Data element comparison processors, methods, systems, and instructions

A processor comprising:

• a decode unit on a die to decode an instruction, the instruction to indicate a first vector register that is to have a first source packed data operand that is to include a first plurality of data elements, one of a second vector register and a memory location that is to have a second source packed data operand that is to include a second plurality of data elements, a first mask register, and a second mask register;
• and
• an execution unit on the die and coupled with the decode unit, the execution unit to perform the instruction to generate and store:
• a first result in the first mask register, the first result to include a different mask bit for each corresponding data element in the first source packed data operand in a same relative position, each mask bit of the first result to indicate whether the corresponding data element in the first source packed data operand equals any of the data elements in the second source packed data operand, wherein each mask bit of the first result is to be set to one to indicate that the corresponding data element in the first source packed data operand equals any of the data elements in the second source packed data operand, or cleared to zero to indicate that the corresponding data element in the first source packed data operand does not equal any of the data elements in the second source packed data operand;
• and
• a second result in the second mask register, the second result to include a different mask bit for each corresponding data element in the second source packed data operand in a same relative position, each mask bit of the second result to indicate whether the corresponding data element in the second source packed data operand equals any of the data elements in the first source packed data operand, wherein each mask bit of the second result is to be set to one to indicate that the corresponding data element in the second source packed data operand equals any of the data elements in the first source packed data operand, or cleared to zero to indicate that the corresponding data element in the second source packed data operand does not equal any of the data elements in the first source packed data operand.

A system comprising:

• a processor including:
• a decode unit to decode instructions of a first instruction set;
• and
• one or more execution units to perform the decoded instructions of the first instruction set;
• a storage device coupled with the processor, the storage device to store:
• a first instruction of a second instruction set, the first instruction to indicate a first source packed data operand that is to have a first plurality of data elements, a second source packed data operand that is to have a second plurality of data elements;
• instructions to convert the first instruction into one or more instructions of the first instruction set, the one or more instructions of the first instruction set, when performed by the processor, are to cause the processor to generate and store:
• a first result mask, the first result mask to include a different mask element for each corresponding data element in the first source packed data operand in a same relative position, each mask element of the first result mask to indicate whether the corresponding data element in the first source packed data operand equals any of the data elements in the second source packed data operand;
• and
• a second result mask, the second result mask to include a different mask element for each corresponding data element in the second source packed data operand in a same relative position, each mask element of the second result mask to indicate whether the corresponding data element in the second source packed data operand equals any of the data elements in the first source packed data operand.