Operation instruction scheduling method and apparatus for nand flash memory device

An electronic device, comprising a processor and a memory, wherein the memory stores computer instructions therein, and the processor executes the following steps by executing the computer instructions:

• performing task decomposition on an operation instruction of a NAND flash memory device, and sending an obtained task to a corresponding task queue;
• sending a current task to a corresponding arbitration queue according to a task type of the current task in the task queue, wherein the task type is determined according to time spent by the task in occupying a NAND interface, and a task that spends shorter time in occupying the NAND interface is assigned a higher task priority;
• determining a priority of an arbitration queue according to a task priority stored in the arbitration queue;
• and
• scheduling a NAND interface for a to-be-executed task in the arbitration queue according to priority information of the arbitration queue.