Apparatus and method and computer program product for configuring impedance of memory interfaces

A non-transitory computer program product for configuring impedance of memory interfaces when executed by a processing unit, wherein the processing unit is coupled to a memory interface, a static random access memory (SRAM) and a calibration interface, the memory interface is coupled to a memory device and comprises a first transmitter and a first receiver, and the memory device comprises a second transmitter and a second receiver, the non-transitory computer program product comprising program code to:

• set a first impedance value associated with an on-die termination (ODT) for the first receiver to a first default value for a first training process, wherein the first receiver of the memory interface of a controller receives signals from the second transmitter of the memory device;
• set a second, impedance value associated with a dr variable resistance for the second transmitter to a second default value for the first training process;
• perform tests for a plurality of first test combinations for the first training process, in which each first test combination comprises a third impedance value associated with a driver variable resistance for the first transmitter and a fourth impedance value associated with an ODT for second receiver, wherein the first transmitter of the memory interface of the controller sends signals to the second receiver of the memory device;
• and
• store a test result for each first test combination in a predefined location of the SRAM, thereby enabling a calibration host to obtain the test result for each first test combination from the SRAM through the calibration interface,
• wherein the first training process comprises a plurality of iterations, and each, iteration corresponding to one first test combination comprises:
• varying the driver variable resistance for the first transmitter according to the corresponding third impedance value;
• varying the ODT for the second receiver according to the corresponding fourth impedance value;
• and
• performing tests when the ODT for the first receiver is fixed to the first default value, and, the driver variable resistance for the second transmitter is fixed to the second default value.

An apparatus for configuring impedance of memory interfaces, comprising:

• a controller, comprising:
• a memory interface, coupled to a memory device, comprising a first transmitter and a first receiver;
• and
• a calibration interface, coupled to a host;
• a static random access memory (SRAM);
• and
• a processing unit, coupled to the memory interface, the calibration interface and the SRAM, arranged to operably set a first impedance value associated with an on-die termination (ODT) for the first receiver to a first default value for a first training process, wherein the first receiver receives signals from a second transmitter of the memory device;
• set a second impedance value associated with a driver variable resistance for the second transmitter to a second default value for the first training process;
• perform tests for a plurality of first test combinations for the first training process, in which each first test combination comprises a third impedance value associated with a driver variable resistance for the first transmitter and a fourth impedance value associated with an ODT for the second receiver, wherein the first transmitter sends signals to a second receiver of the memory device;
• and store a test result for each first test combination in a predefined location of the SRAM, thereby enabling a calibration host to obtain the test result for each first test combination from the SRAM through the calibration interface,
• wherein the first training process comprises a plurality of iterations, and each iteration corresponding to one first test combination comprises:
• varying the driver variable resistance for the first transmitter according to the corresponding third impedance value;
• varying the ODT for the second receiver according to the corresponding fourth impedance value;
• and
• performing the tests when the ODT for the first receiver is fixed to the first default value, and the driver variable resistance for the second transmitter is fixed to the second default value.