Dual processor power saving architecture communications system

A communications system comprising:

• a low power connectivity processor operative to process wireless packets;
• a low power front end comprising a first baseband processor operative to receive wireless packets and a first Media Access Controller (MAC) coupled to the first baseband processor;
• an applications processor;
• a performance front end comprising a second baseband processor operative to receive wireless packets and a second MAC coupled to the second baseband processor;
• and
• a power controller coupled to the low power connectivity processor and to the applications processor;
• the power controller operative to enable the low power connectivity processor and the low power front end upon detection of wireless packets of a first class of packet type, the power controller operative to enable the applications processor and the performance front end upon receipt of wireless packets of a second class of packet type.

A method for wireless communications operative on a communications system comprising a low power front end including a first baseband processor and a first Media Access Controller (MAC) coupled to a low power connectivity processor operative to process wireless packets, a performance front end including a second baseband processor and a second MAC coupled to an applications processor, and a power controller coupled to the low power connectivity processor and to the applications processor, the method comprising:

• receiving a wireless packet on the first MAC;
• examining a packet type field provided by the first MAC;
• and
• enabling power to the applications processor and the performance front end only when the packet type field matches a performance packet type associated with a computational complexity greater than the low power connectivity processor can process, and not enabling power to the applications processor and the performance front end when the packet type field does not match the performance packet type.