Method of clock gate analysis for improved efficiency of electronic circuitry system designs and related systems, methods and devices

A system for analyzing electronic circuitry, comprising:

• a non-transitory storage medium configured to store electronic files of waveforms corresponding to operation of clock gates and gated-devices of an electronic circuitry;
• a processor for processing the electronic files of waveforms stored at the non-transitory storage medium, wherein the processor is configured to:
• identify propagating clock cycles of a clock gate;
• identify idle clock cycles of a gated-device operatively coupled to the clock gate;
• identify wasted propagation clock cycles responsive to an overlap of the propagating clock cycles and the idle clock cycles;
• configure a modified clock gating logic responsive to the wasted propagation clock cycles;
• compare a first activity of the gated-device to a second activity of the gated-device;
• and
• confirm the first activity and the second activity are consistent.

A computer program product, comprising:

• a computer-readable medium;
• and
• instructions stored on the computer-readable medium, the instructions configured to enable a processor to perform operations of:
• identifying propagating clock cycles of a clock gate;
• identifying idle clock cycles of a gated-device operatively coupled to the clock gate;
• identifying wasted propagation clock cycles responsive to an overlap of the propagating clock cycles and the idle clock cycles;
• configuring a modified clock gating logic responsive to the wasted propagation clock cycles;
• comparing a first activity of the gated-device to a second activity of the gated-device;
• and
• confirming the first activity and the second activity are consistent.

A method of analyzing an electronic circuitry design, comprising:

• identifying logic cells comprising a gate-level logic model of an electronic circuitry design;
• generating first simulation commands for simulating the electronic circuitry design responsive to the identified logic cells;
• performing a first simulation responsive to generating the first simulation commands;
• identifying clock gate behavior responsive to performing the first simulation;
• generating second simulation commands for simulating the electronic circuitry design responsive to identifying the clock gate behavior;
• performing a second simulation responsive to generating the second simulation commands;
• collecting dynamic efficiency information for the electronic circuitry design responsive to performing the second simulation;
• and
• scoring one or more of the electronic circuitry design, clock-gates of the electronic circuitry design, and gated-devices of the electronic circuitry design responsive to collecting the dynamic efficiency information.