US 11,112,457 B2 · Dynamic weight selection process for logic built-in self test

Abstract

A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.

Claims18

Dependent claims

A method for testing a logic circuit of a semiconductor chip, the method comprising:

determining a plurality of logic chains of the logic circuit, wherein the logic chains are scan chains;
generating one or more weighted bit chains for testing a first subset of the plurality of logic chains, wherein the one or more weighted bit chains are a series of weighted pseudo-random test patterns;
determining an alternate weighted bit chain for testing a second subset of the plurality of logic chains, and selecting the alternate weighted bit chain wherein the alternate weighted bit chain is a different set/series of the one or more weighted bit chains and wherein the alternate weighted bit chain is selected from a group consisting of:
i) determining proportion of fault coverage and ii) fault observation probability;
executing a logic built-in self test to perform:
testing the first subset of the plurality of logic chains based on the weighted bit chain;
testing the second subset of the plurality of logic chains based on the alternate weighted bit chain.

4 more elements

A computer program product for testing a logic circuit of a semiconductor chip, the computer program product comprising a computer readable storage medium having stored thereon program instructions programmed to perform:

determining a plurality of logic chains of the logic circuit, wherein the logic chains are scan chains;
generating one or more weighted bit chains for testing a first subset of the plurality of logic chains, wherein the one or more weighted bit chains are a series of weighted pseudo-random test patterns;
determining an alternate weighted bit chain for testing a second subset of the plurality of logic chains, and selecting the alternate weighted bit chain wherein the alternate weighted bit chain is a different set/series of the one or more weighted bit chains and wherein the alternate weighted bit chain is selected from a group consisting of:
i) determining proportion of fault coverage and ii) fault observation probability;
executing a logic built-in self test to perform:
testing the first subset of the plurality of logic chains based on the weighted bit chain;
and
testing the second subset of the plurality of logic chains based on the alternate weighted bit chain.

5 more elements

A computer system for testing a logic circuit of a semiconductor chip, the computer system comprising:

a processor set;
and
a computer readable storage medium;
wherein:
the processor set is structured, located, connected and/or programmed to run program instructions stored on the computer readable storage medium;
and
the program instructions include instructions programmed to perform:
determining a plurality of logic chains of the logic circuit, wherein the logic chains are scan chains;
generating one or more weighted bit chains for testing a first subset of the plurality of logic chains, wherein the one or more weighted bit chains are a series of weighted pseudo-random test patterns;
determining an alternate weighted bit chain for testing a second subset of the plurality of logic chains, and selecting the alternate weighted bit chain wherein the alternate weighted bit chain is a different set/series of the one or more weighted bit chains and wherein the alternate weighted bit chain is selected from a group consisting of:
i) determining proportion of fault coverage and ii) fault observation probability;
executing a logic built-in self test to perform:
testing the first subset of the plurality of logic chains based on the weighted bit chain;
and
testing the second subset of the plurality of logic chains based on the alternate weighted bit chain.

12 more elements

Dependencies are inferred from the claim text.

Dynamic weight selection process for logic built-in self test

Life of this patent

Dynamic weight selection process for logic built-in self test

Life of this patent

Abstract

Claims18