Heatsink for co-packaged optical switch rack package

A switch module based on co-packaged optics comprising:

• a rack chassis with a bottom plate extended from a front side to a back side;
• multiple electrically powered fans installed on the back side being configured to generate a forced air flow from the front side to the back side with a certain flow rate;
• a co-packaged optical-electrical module including a processor ASIC chip at a central region of a switch substrate with multiple light engine chiplets commonly mounted along peripheral edges of the switch substrate mounted on the bottom plate;
• a base plate attached on a top of the co-packaged optical-electrical module, the base plate being center-aligned with the central region of the switch substrate and edge-extended parallelly beyond the peripheral edges of the switch substrate in all directions;
• a plurality of fin structures extended upward from the base plate except for a central cavity region, each of the plurality of fin structures having a fin-plane extended along an axial direction from a front edge to a back edge of the base plate except for some trenches shallow in depth across some of the plurality of fin structures and some other trenches deep in depth down to the base plate either along or across some of the plurality of fin structures;
• and
• multiple thermal conductors embedded in the some trenches shallow in depth and the some other trenches deep in depth in the plurality of fin structures, each of the thermal conductors including a pair of top horizontal portions laid in a corresponding pair of the some trenches shallow in depth across some of the plurality of fin structures, at least one bottom horizontal portion laid in the central cavity region of the base plate or in a corresponding one of the some other trenches deep in depth down to the base plate along or across some of the plurality of fin structures, and a pair of vertical portions to connect the pair of top horizontal portions and the at least one bottom horizontal portion, the at least one bottom horizontal portion being brazed to a part of the base plate which is superimposed on either the processor ASIC chip at the central region of the switch substrate or the multiple light engine chiplets mounted along one of the peripheral edges of the switch substrate.

A method of cooling an optical-electrical switch in rack package comprising:

• providing a rack chassis with a bottom plate extended from a front side to a back side;
• generating a forced air flow from the front side to the back side in the rack chassis;
• mounting a co-packaged optical-electrical module on the bottom plate, the co-packaged optical-electrical module including a processor ASIC chip at a central region of a switch substrate with multiple light engine chiplets commonly mounted along peripheral edges of the switch substrate;
• disposing an integrated heatsink on a top of the co-packaged optical-electrical module in the rack chassis, the integrated heatsink comprising,
• a base plate attached to the top of the co-packaged optical-electrical module, the base plate being center-aligned with the central region of the switch substrate and edge-extended parallelly beyond the peripheral edges of the switch substrate in all directions;
• a plurality of fin structures extended upward from the base plate except for a central cavity, each of the plurality of fin structures having a fin-plane extended along an axial direction from a front edge to a back edge of the base plate except for some trenches shallow in depth across some of the plurality of fin structures and some other trenches deep in depth down to the base plate either along or across some of the plurality of fin structures;
• and
• multiple thermal conductors embedded in the some trenches shallow in depth and the some other trenches deep in depth in the plurality of fin structures, each of the multiple thermal conductors including a pair of top horizontal portions laid in a corresponding pair of the some trenches shallow in depth across some of the plurality of fin structures, at least one bottom horizontal portion laid in the central cavity of the base plate or in a corresponding one of the some other trenches deep in depth down to the base plate along or across some of the plurality of fin structures, and a pair of vertical portions to connect the pair of top horizontal portions and the at least one bottom horizontal portion, the at least one bottom horizontal portion being brazed to a part of the base plate which is superimposed on either the processor ASIC chip at the central region of the switch substrate or the multiple light engine chiplets mounted along one of the peripheral edges of the switch substrate.