On-chip resistor trimming to compensate for process variation

A circuit, comprising:

• a first resistive network comprising:
• M resistors having resistances which increase in resistance value R by a multiple of a fixed number Q=2Y, such that a first of the M resistors has a resistance of R*Q=R*2Y, with each subsequent one of the M resistors increasing in value by a multiple of Q, such that the Mth resistor has a resistance of R*Q*M=R*2Y*M;
• M switches respectively associated with the M resistors;
• wherein each of the M resistors is directly electrically coupled between a first node and its associated one of the M switches;
• and
• wherein each of the M switches selectively couples its associated one of the M resistors to a second node;
• and
• a second resistive network comprising:
• P resistors having resistances which increase linearly in resistance value by R, such that a first of the P resistors has a resistance value of R, with each subsequent one of the P resistors increasing in value by R such that the Pth resistor of the P resistors has a resistance value of R*P, wherein P=Q−1;
• P switches respectively associated with the P resistors;
• wherein each of the P resistors is directly electrically coupled between the second node and its associated one of the P switches;
• and
• wherein each of the P switches selectively couples its associated one of the P resistors to a third node.

A resistance trimming circuit, comprising:

• for a trimming resolution of N bits, where X+Y=N:
• a resistive circuit comprising:
• M resistors, where M=2X−1, with each of the M resistors having a resistance that is equal to R*(2Y)*i, with i being an index having a value ranging from 1 to 2X−1, such that a first of the M resistors has a resistance of R*2Y, such that a second of the M resistors has a resistance of R*2Y*2, such that a third of the M resistors has a resistance of R*2Y*3, and such that a last of the M resistors has a resistance of R*2Y*(2X−1);
• M switches respectively associated with the M resistors;
• wherein each of the M resistors is directly electrically coupled between a first node and its associated one of the M switches;
• and
• wherein each of the M switches selectively couples its associated one of the M resistors to a second node.

A resistance trimming circuit, comprising:

• for a trimming resolution of N bits, where X+Y=N:
• a resistive circuit comprising:
• P resistors, where P=2Y−1, with each of the P resistors having a resistance that is equal to R*i, such that a first of the P resistors has a resistance equal to R, such that a last of the P resistors has a resistance equal to R*(2Y−1);
• P switches respectively associated with the P resistors;
• wherein each of the P resistors is directly electrically coupled between a second node and its associated one of the P switches;
• and
• wherein each of the P switches selectively couples its associated one of the P resistors to a third node.