Power management integrated circuit (PMIC), memory module and computing system including a PMIC, and method of operating a memory system

A dynamic random access memory (DRAM) module, comprising:

• a module board;
• a DRAM device mounted to the module board, the DRAM device including a plurality of operating voltage terminals;
• and
• a power management integrated circuit (PMIC) mounted to the module board, the PMIC including a plurality of voltage regulators configured to generate a plurality of operating voltages applied to the respective plurality of operating voltage terminals of the DRAM, the PMIC configured to receive a plurality of feedback voltages of the respective plurality of operating voltages, wherein the voltage regulators are further configured to regulate the respective plurality of operating voltages using the feedback voltages,
• wherein the PMIC includes a monitoring circuit configured to determine a number of times each of the plurality of feedback voltages is outside a respective threshold voltage range, and to store the number of times in a count register.