Low power ideal diode control circuit

An apparatus comprising:

• a pass transistor having a first current terminal coupled to a voltage input terminal, a second current terminal coupled to a voltage output terminal, and a gate terminal;
• an amplifier having:
• a first PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET;
• and
• a second PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the first PFET, and a drain configured to deliver a turn-off signal;
• and
• an output stage configured to regulate the gate of the pass transistor based on a bias signal representing a voltage difference of the voltage input terminal and the voltage output terminal, and configured to turn off the gate of the pass transistor based on the turn-off signal.

An apparatus comprising:

• a pass transistor having a first current terminal coupled to a voltage input terminal, a second current terminal coupled to a voltage output terminal, and a gate terminal;
• an amplifier having:
• a first PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET;
• and
• a second PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the first PFET, and a drain;
• and
• an output stage configured to regulate the gate of the pass transistor based on a bias signal representing a voltage difference of the voltage input terminal and the voltage output terminal, the output stage including:
• a third PFET having a source coupled to the gate of the pass transistor, a gate coupled to the drain of the second PFET, and a drain coupled to a ground terminal;
• an NFET having a drain coupled to the gate of the third PFET, a gate, and a source coupled to the ground terminal;
• and
• a resistor having coupled between the voltage output terminal and the gate of the third PFET.