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US 11,079,641 B2Granted
Display panel and manufacturing method thereof
AssigneeWuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
InventorZesheng Chen
Life of this patent
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Abstract
A display panel and a manufacturing method thereof are provided. The display panel includes a substrate having a semiconductor film layer structure which is provided with an active area, a plurality of data lines disposed on the active area of the transparent substrate, a plurality of scan lines disposed on the active area of the transparent substrate, wherein the scan lines are perpendicular to the data lines, and a plurality of leads electrically connected to the corresponding scan lines, and the leads parallel to the data lines.
Claims13
A display panel, comprising:
- a substrate having a semiconductor film layer structure, wherein the semiconductor film layer structure is provided with a gate driver on array region, an active area, and an integrated circuit region, the gate driver on array region is opposite to the integrated circuit region, and the active area is located between the gate driver on array region and the integrated circuit region, wherein the semiconductor film layer structure comprises:
- a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer, the interlayer insulation layer is disposed between the first metal layer and the second metal layer, the planarization layer is disposed on the second metal layer, and the planarization layer has a plurality of conductive holes;
- a plurality of data lines disposed on the active area of the substrate, wherein the data lines are formed by a patterning process for the second metal layer;
- a plurality of scan lines disposed on the active area of the substrate, wherein the scan lines are perpendicular to the data lines, and the scan lines are formed by a patterning process for the first metal layer;
- and
- a lower transparent conductive layer disposed on the planarization layer, wherein the lower transparent conductive layer is formed into a plurality of leads by a patterning process for the lower transparent conductive layer, the leads are electrically connected to the corresponding scan lines through the conductive holes, and the leads are parallel to the data lines;
- wherein one of the leads misaligns with one of the data lines.
4 more elements
A display panel, comprising:
- a substrate having a semiconductor film layer structure, wherein the semiconductor film layer structure is provided with a gate driver on array region, an active area, and an integrated circuit region, the gate driver on array region is opposite to the integrated circuit region, and the active area is located between the gate driver on array region and the integrated circuit region, wherein the semiconductor film layer structure comprises:
- a gate insulation layer, a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer;
- a plurality of data lines disposed on the active area of the substrate, wherein the data lines are formed from the second metal layer disposed on the interlayer insulation layer;
- a plurality of scan lines disposed on the active area of the substrate, wherein the scan lines are perpendicular to the data lines, and the scan lines are formed from the first metal layer disposed on the gate insulation layer;
- and
- a plurality of leads electrically connected the corresponding scan lines with the gate driver on array region, and the leads are parallel to the data lines, wherein the leads are formed from a lower transparent conductive layer disposed on the planarization layer, and one of the leads misaligns with one of the data lines.
3 more elements
A display panel, comprising:
- a substrate having a semiconductor film layer structure, wherein the semiconductor film layer structure is provided with an active area, wherein the semiconductor film layer structure comprises:
- a gate insulation layer, a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer;
- a plurality of data lines disposed on the active area of the substrate, wherein the data lines are formed from the second metal layer disposed on the interlayer insulation layer;
- a plurality of scan lines disposed on the active area of the substrate, wherein the scan lines are perpendicular to the data lines, and the scan lines are formed from the first metal layer disposed on the gate insulation layer;
- and
- a plurality of leads electrically connected to the corresponding scan lines, and the leads are parallel to the data lines, wherein the leads are formed from a lower transparent conductive layer disposed on the planarization layer, and one of the leads misaligns with one of the data lines.
3 more elements
Dependencies are inferred from the claim text.