Logic built-in self test dynamic weight selection method

A computer program product comprising a non-transitory computer readable storage medium having stored thereon program instructions programmed to perform:

• identifying a scan chain, of a logic circuit, of a semiconductor chip, wherein identifying the scan chain is based on:
• (i) logic built-in self-test (LBSIT), (ii) controls/observes logic network resistance to pseudo-random fault detection and (iii) logic design of the semiconductor chip;
• generating a weighted bit chain for testing the scan chain;
• operating the semiconductor chip using the weighted bit chain as input to the scan chain;
• determining that a fault of the logic circuit has not been tested;
• in response to determining that the fault of the logic circuit has not been tested, dynamically selecting a second weighting factor to generate an alternate weighted bit chain for testing the scan chain, wherein the probability of the first pseudo-random bit is modified by the second weighting factor;
• and
• operating the semiconductor chip using the alternate weighted bit chain as input to the scan chain.

A computer system comprising:

• one or more computer processors;
• one or more computer readable non-transitory storage media;
• and
• program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions, when executed by the one or more computer processors, causing the one or more computer processors:
• to identify a scan chain, of a logic circuit, of a semiconductor chip wherein to identify the scan chain is based on:
• (i) logic built-in self-test (LBSIT), (ii) controls/observes logic network resistance to pseudo-random fault detection and (iii) logic design of the semiconductor chip;
• to generate a weighted bit chain for testing the scan chain;
• to operate the semiconductor chip using the weighted bit chain as input to the scan chain;
• to determine that a fault of the logic circuit has not been tested;
• in response to determine that the fault of the logic circuit has not been tested, dynamically selecting a second weighting factor to generate an alternate weighted bit chain for testing the scan chain, wherein the probability of the first pseudo-random bit is modified by the second weighting factor;
• and
• to operate the semiconductor chip using the alternate weighted bit chain as input to the scan chain.