Entering home state after soft reset signal after address match
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
Claims15
A process of operating an address and instruction controller having states comprising:
- (a) transitioning from a home state to an input address state in response to receiving a test mode select signal in a first state;
- (b) during the input address state, shifting address signals into an address circuit;
- (c) transitioning from the input address state to an address match state in response to receiving a test mode signal of a second state;
- (d) in the address match state, testing for a match between the address signals shifted in and an address in an address circuit;
- (e) transitioning from the address match state to an idle state if the address signals shifted in do not match the address in the address circuit;
- and
- (f) transitioning from the idle state to the home state in response to receiving a soft reset signal.
Dependencies are inferred from the claim text.