Secure wafer inspection and identification

A method for authentication throughout a process flow for fabrication of chips on a wafer, the method comprising the steps of:

• processing a level N of the wafer during which reference structures are placed across the chips at the level N of the wafer;
• performing first overlay and scatterometry measurements of the reference structures at the level N of the wafer;
• inspecting the level N of the wafer;
• processing a level N+1 of the wafer during which the reference structures are placed across the chips at the level N+1 of the wafer;
• performing second overlay and scatterometry measurements at the level N+1 of the wafer of the reference structures placed at the level N of the wafer;
• and
• matching the first overlay and scatterometry measurements of the reference structures at the level N of the wafer to the second overlay and scatterometry measurements of the reference structures at the level N of the wafer for authentication of the wafer that has been inspected.