Floating base silicon controlled rectifier

A whole-chip ESD protection structure, comprising:

• a first and second floating base silicon controlled rectifier each comprising:
• a first conductivity type substrate;
• a second conductivity type well formed in said first conductivity type substrate, said second conductivity type being different than said first conductivity type;
• a first conductivity type heavily doped region formed in said second conductivity type well and coupled to a first node, wherein the first node is the only node coupled within the second conductivity type well;
• and
• a second conductivity type heavily doped region formed in said first conductivity type substrate and coupled to a second node, such that said first conductivity type substrate, said second conductivity type well, said first conductivity type heavily doped region and said second conductivity type heavily doped region forms said floating base silicon controlled rectifier;
• wherein an anode of said first floating base silicon controlled rectifier is electrically connected to a low voltage level, a cathode of said first floating base silicon controlled rectifier and an anode of said second floating base silicon controlled rectifier are electrically connected to an I/O pin, a cathode of said second floating base silicon controlled rectifier is electrically connected to a high voltage level, and the first and second floating base silicon controlled rectifiers are capable of acting as a forward biased diode, the first and second floating base silicon controlled rectifiers have a small turn-on voltage in a range of 0.7 V-1.0 V and the first and second floating base silicon controlled rectifiers show no snapback effect.