Interpolation operational amplifier circuit and display panel

An interpolation operational amplifier circuit, comprising:

• a first power supply input terminal and a second power supply input terminal, wherein a first power supply voltage of the first power supply input terminal is larger than a second power supply voltage of the second power supply input terminal;
• at least two sets of differential input pair transistors, each set of differential input pair transistors comprising a P-type differential input pair transistor composed of P-type transistors and an N-type differential input pair transistor composed of N-type transistors, wherein each differential input pair transistor of the at least two sets of differential input pair transistors comprises a first transistor and a second transistor, a gate electrode of the first transistor of at least one set of the at least two sets of differential input pair transistors is electrically connected to a first input terminal of the interpolation operational amplifier circuit, and a gate electrode of the first transistor of at least another set of the at least two sets of differential input pair transistors is electrically connected to a second input terminal of the interpolation operational amplifier circuit;
• for each differential input pair transistor of the at least two sets of differential input pair transistors, body terminals of the first transistor and the second transistor of the differential input pair transistor are electrically connected to each other to serve as a body terminal of the differential input pair transistor, and source electrodes of the first transistor and the second transistor of the differential input pair transistor are electrically connected to each other to serve as a source electrode of the differential input pair transistor;
• and
• voltage control units each electrically connected to the body terminal of the differential input pair transistor and the source electrode of the differential input pair transistor, and configured to control a voltage of the body terminal of the P-type differential input pair transistor to be smaller than the first power supply voltage of the first power supply input terminal, and/or to control a voltage of the body terminal of the N-type differential input pair transistor to be larger than the second power supply voltage of the second power supply input terminal.