Synchronization with a host processor
AssigneeGraphcore Limited
InventorsDaniel John Pelham Wilkinson, Stephen Felix, Matthew David Fyles, Richard Luke Southwell Osborne
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AssigneeGraphcore Limited
InventorsDaniel John Pelham Wilkinson, Stephen Felix, Matthew David Fyles, Richard Luke Southwell Osborne
Estimating the term…
A processing system comprising: a subsystem for acting as a work accelerator to a host processor, the subsystem comprising an arrangement of tiles; and an interconnect for communicating between the tiles and connecting the subsystem to the host. The interconnect comprises synchronization logic to coordinate barrier synchronizations between a group of the tiles. The synchronization logic comprises a host sync proxy module, comprising a counter written with a number of credits by the host processor, and being configured to automatically decrement the number of credits each time one of the barrier synchronizations requiring host involvement is performed. When the number of credits in the counter is exhausted, the barrier is not released until a further write from the host to the host sync proxy module, but when the number is credits in the counter is not exhausted the barrier is released without a separate write from the host.
A processing system comprising:
A method of operating a processing system comprising a subsystem for acting as a work accelerator to a host processor, the subsystem comprising an arrangement of tiles each comprising a respective execution unit for executing machine code, and the processing system further comprising an interconnect for communicating between the tiles and for connecting the subsystem to an external host processor via an external interconnect;
Dependencies are inferred from the claim text.