Strong arm latch with wide common mode range
AssigneeIntel Corporation
InventorsRaymond Chong, Bee Min Teng, Christopher Mozak
Life of this patent
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Abstract
Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.
Claims26
An apparatus comprising:
- a first sampler to sample an input with a first clock, and to provide a sampled output on a first node;
- a strong arm latch (SAL) to receive the first sampled output on the first node, and to sample the sampled output according to a second clock;
- a first digital-to-analog converter (DAC) coupled to the first node, wherein the first DAC is to adjust a common mode of the first sampled output according to a digital control to the DAC, wherein the first DAC is to adjust the common mode higher than a power supply voltage for the SAL;
- a second sampler to sample a second input with the first clock, and to provide a second sampled output on a second node;
- and
- a second DAC coupled to the second node, wherein the second DAC is to adjust a common mode of the second sampled output according to the digital control to the second DAC;
- wherein the SAL comprises:
- a first differential circuitry to receive the first and second sampled inputs;
- a second differential circuitry to receive the first and second sampled inputs;
- and
- a latch circuitry coupled to the first and second differential circuitries.
An apparatus comprising:
- a differential strong arm latch (SAL) to receive two sampled inputs;
- and
- first and second digital-to-analog converters (DACs) coupled to the differential SAL, wherein the first and second DACs are to adjust common modes of the two sampled inputs according to a first and second digital controls to the first and second DACs;
- and
- a latch coupled to an output of the differential SAL, wherein the differential SAL is to receive a first clock separate from a second clock which is used to generate the two sampled inputs.
A system comprising:
- a memory;
- a processor coupled to the memory, the processor having a receiver including a sense amplifier latch, wherein the sense amplifier latch comprises:
- a first sampler to sample an input with a first clock, and to provide a sampled output on a first node;
- a strong arm latch (SAL) to receive the first sampled output on the first node, and to sample the first sampled output according to a second clock;
- a first digital-to-analog converter (DAC) coupled to the first node, wherein the first DAC is to adjust a common mode of the first sampled output according to a digital control to the DAC, wherein the first DAC is to adjust the common mode higher than a power supply voltage for the SAL;
- a second sampler to sample a second input with the first clock, and to provide a second sampled output on a second node;
- and
- a second DAC coupled to the second node, wherein the second DAC is to adjust a common mode of the second sampled output according to the digital control to the second DAC;
- wherein the SAL comprises:
- a first differential circuitry to receive the first and second sampled inputs;
- a second differential circuitry to receive the first and second sampled inputs;
- and
- a latch circuitry coupled to the first and second differential circuitries;
- and
- a wireless interface to allow the processor to communicate with another device.
Dependencies are inferred from the claim text.