Clock multiplier
AssigneeNuvoton Technology Corporation
InventorsYuan-Po Cheng, Pao-Shu Chang
Life of this patent
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Abstract
A clock multiplier is provided. The clock multiplier includes a delay line, an output clock generator, and a delay controller. The delay line receives an input clock and delays the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock. The output clock generator performs a logic operation on the input clock and a portion of the delayed clocks to generate an output clock. A frequency of the output clock is an integer multiple of a frequency of the input clock. The delay controller adjusts the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.
Claims20
A clock multiplier comprising:
- a delay line configured to receive an input clock and delay the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock, wherein the input clock, the delayed clocks, and the feedback clock have a same clock cycle;
- an output clock generator coupled to the delay line and configured to receive the input clock and the delayed clocks and perform a logic operation on the input clock and a portion of the delayed clocks to generate an output clock, wherein a frequency of the output clock is 2L times a frequency of the input clock, where L is a positive integer;
- and
- a delay controller coupled to the delay line and configured to receive the input clock and the feedback clock and adjust the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.
Dependencies are inferred from the claim text.