Hardware acceleration using a self-programmable coprocessor architecture

An apparatus for hardware acceleration using a self-programmable coprocessor architecture configured to carry out the steps of:

• determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence;
• responsive to determining that the instruction cache comprises an accelerable instruction sequence:
• instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction;
• and
• receiving, from the accelerator complex, a result of the complex instruction;
• responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence:
• determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image;
• and
• synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence.

A computer program product for hardware acceleration using a self-programmable coprocessor architecture, the computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

• determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence;
• responsive to determining that the instruction cache comprises an accelerable instruction sequence:
• instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction;
• and
• receiving, from the accelerator complex, a result of the complex instruction;
• responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence:
• determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image;
• synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence;
• and
• verifying the synthesized accelerator image.