Method, apparatus and system for dynamic control of clock signaling on a bus
AssigneeIntel Corporation
InventorsKenneth P. Foust, Amit Kumar Srivastava, Nobuyuki Suzuki
Life of this patent
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Abstract
In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.
Claims19
An apparatus comprising:
- a host controller to couple to an interconnect to which a plurality of devices may be coupled, the host controller including a clock control circuit to cause the host controller to communicate a clock signal on a clock line of the interconnect, the clock control circuit to receive an indication that a first device of the plurality of devices is to send information to the host controller and to dynamically release control of the clock line of the interconnect in response to an in-band interrupt from the first device to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information, wherein the first device is a clock source capable device comprising a slave device.
At least one computer readable storage medium comprising instructions that when executed enable a system to:
- receive, in a host controller of a bus, a request for a slave device to communicate information on the bus;
- determine whether the slave device has a clock source capability;
- in response to a determination that the slave device has the clock source capability, release control of a clock line of the bus to the slave device;
- and
- reclaim the control of the clock line of the bus after the slave device communicates the information.
A system comprising:
- a first device coupled to a host controller via a bus to which a plurality of devices may be coupled, wherein the first device includes a first clock generation circuit to generate a first clock signal, the first device to send the first clock signal on the bus when granted clock source permission by the host controller;
- the host controller coupled to the first device and having a host clock control circuit, in response to a determination that the first device has information to send to the host controller, to dynamically hand-off clock control for the bus from the host controller to the first device to enable the first device to send the information and the first clock signal via the bus;
- and
- a non-volatile storage to store configuration information for the plurality of devices, the configuration information to indicate whether each of the plurality of devices is a clock source capable device.
Dependencies are inferred from the claim text.