Multi-threaded architecture for memory controller data paths

An article of manufacture comprising:

• N processing cores, wherein N is an integer greater than 1;
• M memory banks, wherein M is an integer greater than or equal to 1;
• and
• a memory controller configured to enable the N processing cores to access the M memory banks, wherein the memory controller is configured to:
• receive a sequence of one or more access requests from each of one or more of the processing cores, wherein each access request is a request for access by the corresponding processing core to a specified memory bank;
• and
• process access requests from one or more of the processing cores to generate a current sequence of one or more granted access requests to each of one or more of the memory banks, wherein:
• for each processing core, the article comprises first and second buffers, each buffer configured to store an access request;
• when an access request from the first buffer is granted, the first buffer is configured to receive a new access request and processing is performed to determine whether to grant an access request stored in the second buffer;
• and
• when an access request from the second buffer is granted, the second buffer is configured to receive a new access request and processing is performed to determine whether to grant an access request stored in the first buffer.