Techniques for managing access to hardware accelerator memory

A method to provide coherence bias for accessing accelerator memory, the method comprising:

• receiving a request to access a logic device memory from a logic device communicatively coupled to the logic device memory, the logic device communicatively coupled to at least one processor;
• determining a bias mode associated with the request based on bias information stored in the logic device memory;
• and
• providing the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode.

A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of a computing device to provide coherence bias for accessing accelerator memory, the instructions to cause the computing device to:

• receive a request to access a logic device memory from a logic device communicatively coupled to the logic device memory, the logic device communicatively coupled to at least one processor;
• determine a bias mode associated with the request based on bias information stored in the logic device memory;
• and
• provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode.