Enhanced address space layout randomization

A method comprising:

• generating a page table associated with a memory, wherein the page table includes a plurality of page table entries;
• flagging each page table entry in the plurality of page table entries as in a valid state;
• instantiating the page table with a first page table entry and a second page table entry of the plurality of page table entries associated with a first memory address of a plurality of memory addresses and a second memory address of the plurality of memory addresses respectively such that the first memory address and the second memory address are allocated;
• flagging the first memory address's and the second memory address's access rights as accessible;
• associating a plurality of unused page table entries of the plurality of page table entries, including a decoy page table entry, to a decoy address of the plurality of memory addresses;
• writing first data to the first memory address;
• and
• after writing the first data to the first memory address, and while the first page table entry remains flagged as valid and also remains flagged as accessible:
• deallocating the first memory address;
• and
• updating the first page table entry to reference the decoy address such that an access timing of the decoy address is the same as an access timing of the second memory address, wherein the decoy address comprises an address that returns a page fault.

A system comprising:

• a memory including a plurality of memory addresses, wherein at least one of the plurality of memory addresses is a decoy address;
• a page table including a plurality of page table entries, wherein each page table entry in the page table is flagged as valid and each page table entry is associated with a memory address of the plurality of memory addresses;
• a memory manager on one or more processors executing to:
• create a first page table entry of the plurality of page table entries referencing a first memory address of the plurality of memory addresses such that the first memory address is allocated;
• flag the first memory address's access rights as accessible;
• write first data to the first memory address, and after writing the first data to the first memory address, and while the first page table entry remains flagged as valid and also remains flagged as accessible:
• receive a command to delete the first data;
• deallocate the first memory address;
• update the first page table entry to reference the decoy address of the plurality of memory addresses such that an access timing of the decoy address is the same as an access timing of a second memory address, wherein the decoy address comprises an address that returns a page fault;
• receive a request to access the first page table entry;
• and
• respond to the request with a rejection.