Integrated circuit and data processing system supporting address aliasing in an accelerator

A method of data processing in a coherent data processing system including a system memory, the method comprising:

• host attach logic communicating memory access requests with the coherent data processing system via a first communication interface and communicating, via a second communication interface, memory access requests and request responses with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory;
• the host attach logic recording, in a real address-based directory inclusive of contents of the accelerator cache, data from the system memory accessed by the accelerator unit, wherein the recording includes assigning entries in the real address-based directory based on real addresses utilized to identify storage locations in the system memory;
• and
• the host attach logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, providing the accelerator unit a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

A design structure tangibly embodied in a storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• host attach logic for a coherent data processing system including a system memory, the host attach logic including:
• a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;
• a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system;
• a real address-based directory inclusive of contents of the accelerator cache, wherein the real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory;
• and
• request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface, wherein the request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides the accelerator unit a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.