System, apparatus and method for selective enabling of locality-based instruction handling

A system comprising:

• a processor having a cache hierarchy including one or more cache memories and a core to process a first memory access instruction having a no-locality hint to indicate non-locality of data associated with the first memory access instruction;
• a memory controller to issue requests to a system memory, the memory controller including a locality controller to receive the first memory access instruction and to selectively handle the first memory access instruction with locality based at least in part on a locality prediction for the first memory access instruction, wherein in response to a second memory access instruction having the no-locality hint, the memory controller is to issue a request to the system memory for a partial width of data and bypass storage of the partial width of data in the cache hierarchy;
• and
• the system memory coupled to the memory controller.