Data coherency manager with mapping between physical and virtual address spaces
AssigneeImagination Technologies Limited
InventorsMartin John Robinson, Mark Landers
Life of this patent
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AssigneeImagination Technologies Limited
InventorsMartin John Robinson, Mark Landers
Estimating the term…
A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination.
A coherency manager for receiving physically addressed snoop requests, the snoop requests being addressed in a physical address space and relating to a virtually addressed cache memory addressable using a virtual address space, the cache memory having a plurality of virtually addressed coherent cachelines, the coherency manager comprising:
A method for processing physically addressed snoop requests, the snoop requests being addressed in a physical address space and relating to a virtually addressed cache memory having a plurality of virtually addressed coherent cachelines addressable using a virtual address space, the method comprising:
A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a coherency manager for receiving physically addressed snoop requests, the snoop requests being addressed in a physical address space and relating to a virtually addressed cache memory addressable using a virtual address space, the cache memory having a plurality of virtually addressed coherent cachelines, the coherency manager comprising:
Dependencies are inferred from the claim text.