Error correction circuit and memory system

A memory system comprising:

• a memory;
• and
• an error correction circuit to perform error correction of read data read from the memory, the read data comprising a plurality of bits, wherein the error correction circuit comprises:
• a syndrome calculator to calculate syndrome information of the read data;
• an error position calculator to calculate error position information of the read data based on the syndrome information;
• a holder to hold the syndrome information or the error position information at a predetermined timing;
• an error detection determiner to determine whether an error of the read data is correctly, detected, based on syndrome information calculated by inputting error-corrected data based on the error position information to the syndrome calculator;
• and
• an error corrector to output the read data after correcting the error of the read data based on information held by the holder when it is determined by the error detection determiner that the error is correctly detected, and to output the read data with no error correction when it is determined by the error detection determiner that the error is not correctly detected.