Memory device and method for handling interrupts thereof

A memory device, comprising:

• a memory cell array;
• a monitoring circuit, configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array;
• an event-checking circuit, configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit;
• and
• a control logic, configured to control the memory cell array according to a command from a processor, wherein the control logic comprises a mode register that pre-records a plurality of operation modes of the memory cell array and a status of the interrupt event corresponding to each event parameter,
• wherein in response to the event-checking circuit determining to assert the interrupt signal, the event-checking circuit directly transmits the interrupt signal to the processor via a physical interrupt pin of the memory device, so that the processor handles the one or more interrupt events of the memory device according to the interrupt signal,
• wherein in response to the processor having handled each interrupt event sequentially, the processor changes the status of each interrupt event in the mode register to a normal status.