Execution unit

A method of operating an execution unit in a processor, the execution unit comprising a hardware module having a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions of input values, wherein the processing pipeline comprises a plurality of stages through which each calculation for evaluating a given mathematical function progresses to an end result, the method comprising:

• performing, at each of a plurality of processing circuits in the processing pipeline, an operation on one or more values to provide a result during at least one stage of the plurality of stages, wherein the processing circuits include a plurality of multiplier circuits;
• operating a first multiplier circuit of the plurality of multiplier circuits and a second multiplier circuit of the plurality of multiplier circuits in parallel such that at a same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform processing of one or more values;
• processing, at a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, outputs from the first multiplier circuit and the second multiplier circuit;
• performing processing associated with a first mathematical function, at a first time, by the first multiplier circuit;
• and
• performing processing associated with a second mathematical function, at the first time, by the third multiplier circuit.

An execution unit for a processor, the execution unit comprising a hardware module having a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions of input values, wherein the processing pipeline comprises a plurality of stages through which each calculation for evaluating a given mathematical function progresses to an end result, the execution unit comprising:

• a first multiplier circuit and a second multiplier circuit arranged in parallel, such that at a first stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit multiply together two or more values to produce multiplication results during the first stage;
• and
• a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, wherein the third multiplier circuit is configured to multiply the multiplication results from the first multiplier circuit and the second multiplier circuit,
• wherein at least one of the first multiplier circuit and the second multiplier circuit is configured to, at a first time, perform processing associated with a first mathematical function, and the third multiplier circuit is configured to, at the first time, perform processing associated with a second mathematical function different to the first mathematical function.