Branch target look up suppression

A method of operating a data processing apparatus, the method comprising the steps of:

• fetching a block of instructions from memory;
• performing branch prediction, comprising processing the block of instructions and providing an indication of a predicted next block of instructions to be fetched from memory, the performing branch prediction comprising the steps of:
• storing in main branch target storage branch target predictions for branch instructions in the block of instructions;
• caching in secondary branch target storage branch target predictions from the main branch target storage;
• initiating a look-up in the secondary branch target storage in parallel with a look-up in the main branch target storage,
• wherein the main branch target storage is set-associative and an entry in the main branch target storage corresponding to the block of instructions comprises multiple ways, wherein each way of the multiple ways is configured to store a branch target prediction for one branch instruction in the block of instructions;
• storing a way prediction indicating which of the multiple ways contain branch target predictions for the predicted next block of instructions;
• storing a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage;
• and
• suppressing the look-up in the main branch target storage for the predicted next block of instructions in response to an active value of the flag,
• generating a prediction of whether each of the branch instructions in the block of instructions will be taken or not-taken, and wherein the predicted next block of instructions to be processed:
• begins at the branch target prediction for a first branch instruction in the block of instructions predicted to be taken by the branch outcome prediction circuitry;
• and
• begins at a next sequential instruction after the block of instructions, when the branch target prediction does not predict any taken branch instructions in the block of instructions;
• storing the way prediction and the flag in an entry of way prediction storage associated with the block of instructions when the predicted next block of instructions sequentially follows the block of instructions,
• reading out entries in parallel from the secondary branch target storage and the way prediction storage at a first stage of multiple pipelined stages, and
• responsive to the generated prediction, selecting between the entries read out in parallel from the secondary branch target storage and the way prediction storage.

An apparatus comprising:

• instruction fetch circuitry to fetch a block of instructions from memory;
• branch prediction circuitry to process the block of instructions and provide the instruction fetch circuitry with an indication of a predicted next block of instructions to be retrieved from memory, the branch prediction circuitry comprising:
• main branch target storage to store branch target predictions for branch instructions in the block of instructions;
• and
• secondary branch target storage to cache the branch target predictions from the main branch target storage, wherein the branch prediction circuitry is configured to initiate a look-up in the secondary branch target storage in parallel with a look-up in the main branch target storage,
• wherein the main branch target storage is set-associative and an entry in the main branch target storage corresponding to the block of instructions comprises multiple ways, wherein each way of the multiple ways is configured to store a branch target prediction for one branch instruction in the block of instructions;
• and
• wherein the branch prediction circuitry is arranged to store a way prediction for which of the multiple ways contain the branch target predictions for the predicted next block of instructions and to store a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage,
• and wherein the branch prediction circuitry is responsive to an active value of the flag to suppress the look-up in the main branch target storage for the predicted next block of instructions,
• wherein the branch prediction circuitry comprises branch outcome prediction circuitry to generate a prediction of whether each of the branch instructions in the block of instructions will be taken or not-taken, and wherein the predicted next block of instructions to be processed:
• begins at the branch target prediction for a first branch instruction in the block of instructions predicted to be taken by the branch outcome prediction circuitry;
• and
• begins at a next sequential instruction after the block of instructions, when the branch target prediction does not predict any taken branch instructions in the block of instructions,
• wherein the branch prediction circuitry comprises multiple pipelined stages, wherein the multiple pipelined stages comprise at least two pipelined stages following the branch outcome prediction circuitry, wherein the at least two pipelined stages comprises a first stage following the branch outcome prediction circuitry and a second stage following the first stage, and wherein each pipelined stage holds information relating to a single block of instructions,
• wherein the branch prediction circuitry comprises update circuitry responsive to replacement of an entry in the secondary branch target storage for a later block of instructions in the first stage to invalidate a way prediction corresponding to an earlier block of instructions in the second stage.