Per-lane dynamic indexing in temporary registers

A system comprising:

• a processor core comprising:
• one or more execution unit circuits, each configured to access one or more pieces of data;
• one or more local register file circuits, each associated with a respective execution unit and each configured to store data;
• and
• a main register circuit, the main register circuit comprising a local index register circuit configured to store, for each local register file, an active index value, and wherein configured to, in response to a request from a control circuit to access a target execution unit circuit, supply the active index value associated with the target execution unit circuit;
• and
• an off-core memory circuit configured to store data.

An apparatus comprising:

• a plurality of execution unit circuits, each configured to access one or more pieces of data;
• a plurality of local register file circuits, each associated with a respective execution unit and each configured to store pieces of data;
• and
• a main register circuit comprising:
• a main register file circuit configured to store data for at least part of the plurality of execution unit circuits, and
• a local index register circuit configured to identify an active storage location in the plurality of local register files, and
• a control circuit configured to:
• issue an instruction to a target execution unit circuit, and
• instruct the local index register circuit to access, at the active storage location, the local register file associated with the target execution unit circuit.