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US 11,029,953 B2Granted
Branch prediction unit in service of short microcode flows
AssigneeIntel Corporation
InventorsMichael Mishaeli, Ido Ouziel, Jared Warner Stark, IV
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AssigneeIntel Corporation
InventorsMichael Mishaeli, Ido Ouziel, Jared Warner Stark, IV
Estimating the term…
Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.
A processor comprising:
A method performed by a processor having a branch prediction unit (BPU) and a pipeline, the method comprising:
A non-transitory machine-readable medium containing code to which a processor comprising a branch prediction unit (BPU) and a pipeline is to respond by:
Dependencies are inferred from the claim text.