Performing processing using hardware counters in a computer system

A computer program product to facilitate processing of a computer system, the computer program product comprising:

• a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
• in preparation for greatest common divisor (GCD) processing of the computer system storing, a first variable of the GCD processing in a first redundant binary representation and a second variable of the GCD processing in a second redundant binary representation, each of the first and second redundant binary representations comprising a respective sum term and a respective carry term, wherein a numerical value being represented by a redundant binary representation that includes a respective sum term and a respective carry term is equal to a sum of that sum term and that carry term of that redundant binary representation;
• performing redundant arithmetic operations of the GCD processing on the first variable and the second variable using one or more hardware counters, of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form, wherein the redundant arithmetic operations comprise,
• inputting each of the sum term of the first redundant binary representation and the sum term of the second redundant binary representation into a respective one of the one or more hardware counters;
• inputting the carry term of the first redundant binary representation, the carry term of the second redundant binary representation, and a modulus into inverter hardware, the inverter hardware performing bitwise inversions to produce a bitwise-inverted carry term of the first redundant binary representation, bitwise-inverted carry term of the second redundant binary representation, and bitwise-inverted modulus;
• inputting the bitwise-inverted carry term of the first redundant binary representation, the bitwise-inverted carry term of the second redundant binary representation, and the bitwise-inverted modulus into first selection hardware that selectively inputs the bitwise-inverted carry term of the first redundant binary representation, the bitwise inverted carry term of the second redundant binary representation, and the bitwise-inverted modulus into the one or more hardware counters;
• inputting to second selection hardware:
• (i) output of the one or more hardware counters, the output of the one or more hardware counters comprising output first and second sum terms and output first and second carry terms, and (ii) the sum and carry terms of the first redundant binary representation and the sum and carry terms of the second redundant binary representation, wherein the second selection hardware selects between the (i) output of the one or more hardware counters and (ii) the sum and carry terms of the first redundant binary representation and the sum and carry terms of the second redundant binary representation;
• and
• using shift hardware to selectively perform shift operations on output of the second selection hardware;
• and
• using output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing.

A computer system comprising:

• a memory;
• and
• a processor in communication with the memory, wherein the computer system is configured to perform a method to facilitate processing of the computer system, the method comprising:
• in preparation for greatest common divisor (GCD) processing of the computer system, storing, a first variable of the GCD processing in a first redundant binary representation and a second variable of the GCD processing in a second redundant binary representation, each of the first and second redundant binary representations comprising a respective sum term and a respective carry term, wherein a numerical value being represented by a redundant binary representation that includes a respective sum term and a respective carry term is equal to a sum of that sum term and that carry term of that redundant binary representation;
• performing redundant arithmetic operations of the GCD processing on the first variable and the second variable using one or more hardware counters, of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form, wherein the redundant arithmetic operations comprise:
• inputting each of the sum term of the first redundant binary representation and the sum term of the second redundant binary representation into a respective one of the one or more hardware counters;
• inputting the carry term of the first redundant binary representation, the carry term of the second redundant binary representation, and a modulus into inverter hardware, the inverter hardware performing bitwise inversions to produce a bitwise-inverted carry term of the first redundant binary representation, bitwise-inverted carry term of the second redundant binary representation, and bitwise-inverted modulus;
• inputting the bitwise-inverted carry term of the first redundant binary representation, the bitwise-inverted carry term of the second redundant binary representation, and the bitwise-inverted modulus into first selection hardware that selectively inputs the bitwise-inverted carry term of the first redundant binary representation, the bitwise-inverted carry term of the second redundant binary representation, and the bitwise-inverted modulus into the one or more hardware counters;
• inputting to second selection hardware:
• (i) output of the one or more hardware counters, the output of the one or more hardware counters comprising output first and second sum terms and output first and second carry terms, and (ii) the sum and carry terms of the first redundant binary representation and the sum and carry terms of the second redundant binary representation, where the second selection hardware selects between the (i) output of the one or more hardware counters and (ii) the sum and carry terms of the first redundant binary representation and the sum and carry terms of the second redundant binary representation;
• and
• using shift hardware to selectively perform shift operations on output of the second selection hardware;
• and
• using output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing.