Reduce system active power based on memory usage patterns

A method of operating a memory device, the method comprising:

• queueing requests to access the memory using a command queue of the memory device;
• determining whether the queued access requests are to sequential addresses of a memory array or to random addresses of the memory array;
• reducing an operating rate of one or more first components of the memory device when the queued access requests are to sequential addresses of the memory array, wherein reducing an operating rate of the one or more first components includes reducing a frequency of a clock signal of the one or more first components and maintaining a frequency of a clock signal of the one or more second components when the queued access requests are to sequential addresses of the memory array;
• and
• reducing an operating rate of one or more second components of the memory device when the queued access requests are to random addresses of the memory array, wherein reducing an operating rate of the one or more second components includes reducing a frequency of a clock signal of the one or more second components and maintaining a frequency of a clock signal of the one or more first components when the queued access requests are to random addresses of the memory array.

A non-transitory computer readable storage medium comprising instructions configured to cause a memory control unit of a memory device to:

• queue requests to access the memory using a queue of the memory device;
• determine whether the queued access requests are to sequential addresses of a memory array or to random addresses of the memory array;
• reduce an operating rate of one or more first components of the memory device when the queued access requests are to sequential addresses of the memory array;
• and
• reduce an operating rate of one or more of error correction code (ECC) circuitry and a flash controller of the memory control unit when the queued access requests are to random addresses of the memory array.

A memory device comprising:

• a memory array including memory cells;
• a communication interface configured for communicating with a host;
• and
• a memory control unit operatively coupled to the memory array and the communication interface, and including a queue, the memory control unit configured to:
• store requests to access the memory in the queue;
• determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array using one or more of a command chunk size or an address range of the memory access requests;
• reduce an operating rate of a first component of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, wherein the first component is a processor, and the memory control unit is configured to reduce a frequency of a clock signal of the processor when the queued memory access requests are to sequential addresses of the memory array;
• and
• reduce an operating rate of a second component of the memory control unit when the queued memory access requests are to random addresses of the memory array, wherein the second component includes error correction code (ECC) circuitry, and the memory control unit is configured to reduce a frequency of a clock signal of the ECC circuitry when the queued memory access requests are to random addresses of the memory array.