Memory controller, memory system, and information processing system

A memory system, comprising:

• a plurality of memories;
• a memory write control unit that includes:
• a first memory request/address transmitting unit configured to generate a write request for a specific memory of the plurality of memories based on a write command from a computer;
• an error correcting code generation unit configured to generate an error correcting code for write data related to the write request for the specific memory;
• and
• a busy signal generation unit configured to generate, as a data processing state, a busy signal for each of the plurality of memories, wherein the busy signal of each of the plurality of memories indicates a corresponding status of generation of the error correcting code for the write data for each of the plurality of memories;
• and
• a memory read control unit that includes:
• a read command selection unit configured to set a priority of a read command from the computer for each of the plurality of memories based on the generated busy signal, wherein the priority of the read command is set high for the specific memory, among the plurality of memories, for which the busy signal indicates the generation of the error correcting code;
• and
• a second memory request/address transmitting unit configured to generate a read request for the specific memory of the plurality of memories based on the set priority and the read command.

An information processing system, comprising:

• a plurality of memories;
• a computer;
• a memory write control unit that includes:
• a first memory request/address transmitting unit configured to generate a write request for a specific memory of the plurality of memories based on a write command from the computer;
• an error correcting code generation unit configured to generate an error correcting code for write data related to the write request for the specific memory;
• and
• a busy signal generation unit configured to generate, as a data processing state, a busy signal for each of the plurality of memories, wherein the busy signal of each of the plurality of memories indicates a corresponding status of generation of the error correcting code for the write data for each of the plurality of memories;
• and
• a memory read control unit that includes:
• a read command selection unit configured to set a priority of a read command from the computer for each of the plurality of memories based on the generated busy signal, wherein the priority of the read command is set high for the specific memory, among the plurality of memories, for which the busy signal indicates the generation of the error correcting code;
• and
• a second memory request/address transmitting unit configured to generate a read request for the specific memory of the plurality of memories based on the set priority and the read command.