US 11,029,847 B2Granted

Method and system for shared direct access storage

AssigneeHewlett Packard Enterprise Development LP

InventorsKirill Malkin, Steve Dean, Michael Woodacre, Eng Lim Goh

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Abstract

In high performance computing, the potential compute power in a data center will scale to and beyond a billion-billion calculations per second (“Exascale” computing levels). Limitations caused by hierarchical memory architectures where data is temporarily stored in slower or less available memories will increasingly limit high performance computing systems from approaching their maximum potential processing capabilities. Furthermore, time spent and power consumed copying data into and out of a slower tier memory will increase costs associated with high performance computing at an accelerating rate. New technologies, such as the novel Zero Copy Architecture disclosed herein, where each compute node writes locally for performance, yet can quickly access data globally with low latency will be required. The result is the ability to perform burst buffer operations and in situ analytics, visualization and computational steering without the need for a data copy or movement.

Claims12

Dependent claims

A method comprising:

receiving information relating to processing a function;
allocating a first processor of a first node to perform a first task associated with the function, wherein the first node is separated from a non-volatile memory by a switch included in a first fabric, the switch being directly connected to the non-volatile memory by a local bus interface of the non-volatile memory;
when performing the first task, transferring, by the first processor through the first fabric using the switch, data from a node memory of the first node through a local bus interface of the first node to the non-volatile memory via direct memory access (DMA) of the non-volatile memory by the first processor;
allocating a second processor of a second node to perform a second task associated with the function, wherein the second node is separated from the non-volatile memory by the switch or by another switch included in the first fabric, the another switch being directly connected to the non-volatile memory;
when performing the second task, receiving, by the second processor through a local bus interface of the second node and through the first fabric using the switch or the another switch, data into a node memory of the second node from the non-volatile memory via DMA of the non-volatile memory by the second processor;
communicating, between the second node and the first node, through a second fabric of a type different from the first fabric, wherein the communicating through the second fabric is between a fabric interface of the first node and a fabric interface of the second node;
and
generating an output of the function, wherein the output of the function is accessible by an external computing device after the output is generated,
wherein the allocating of the first processor to perform the first task and the allocating of the second processor to perform the second task are by a data node,
sending, by the data node to the first node and the second node, a device driver for accessing the non-volatile memory;
executing the device driver at the first node and the second node when accessing the non-volatile memory in performing the first task and the second task, respectively;
executing, by the data node, a further device driver, wherein the device driver sent to the first node and the second node has less functionality than the further device driver;
and
configuring, by the further device driver executed by the data node, the non-volatile memory.

11 more elements

A non-transitory computer readable storage medium comprising instructions that upon execution cause a coordinator node to:

receive information relating to processing a function;
allocate a first processor of a first node to perform a first task associated with the function, wherein the first node is separated from a non-volatile memory by a switch included in a first fabric, the switch being directly connected to the non-volatile memory by a local bus interface of the non-volatile memory, and the first processor when performing the first task transfers, through the first fabric using the switch, data from a node memory of the first node through a local bus interface of the first node to the non-volatile memory via direct memory access (DMA) of the non-volatile memory by the first processor;
allocate a second processor of a second node to perform a second task associated with the function, the second node separated from the non-volatile memory by the switch or by another switch included in the first fabric, the another switch being directly connected to the non-volatile memory, wherein the second processor when performing the second task receives, through a local bus interface of the second node and through the first fabric using the switch or the another switch, data into a node memory of the second node from the non-volatile memory via DMA of the non-volatile memory by the second processor, and wherein the second node and the first node are to communicate with each other through a second fabric of a different type from the first fabric, the communicating through the second fabric being between a fabric interface of the first node and a fabric interface of the second node;
send, from the coordinator node to the first node and the second node, a device driver for accessing the non-volatile memory, to cause execution of the device driver at the first node and the second node when accessing the non-volatile memory in performing the first task and the second task, respectively;
execute, at the coordinator node, a further device driver, wherein the device driver sent to the first node and the second node has less functionality than the further device driver;
and
configure, by the further device driver executed by the coordinator node, the non-volatile memory.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/353,413Filed 16 Nov 2016 · us provisional application
Priority: 16 Nov 2015
Published: US 2017/0139607 A118 May 2017
Granted: 8 Jun 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 3/0607
Improving or facilitating administration, e.g. storage management: by facilitating the process of upgrading existing storage systems, e.g. for…
G06F 3/0635
Configuration or reconfiguration of storage systems: by changing the path, e.g. traffic rerouting, path reconfiguration
G06F 3/0685
Plurality of storage devices: hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
G06F 3/0688
Plurality of storage devices: non-volatile semiconductor memory arrays

Family

Application62/255,832Us provisional application · filed 16 Nov 2015
US 2017/0139607 A1Pre-grant publication · published 18 May 2017
US 11,029,847 B2This patent

From the US filing history. Foreign family members aren’t listed.

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